Method of correlating silicon stress to device instance parameters for circuit simulation
US7542891B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2006 |
| Grant date | Jun 2, 2009 |
| Priority date | — |
| Expiry date | Oct 18, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Roughly described, standard SPICE models can be modified by substituting a different stress analyzer to better model the stress adjusted characteristics of a transistor. A first, standard, stress-sensitive, transistor model is used to develop a mathematical relationship between the first transistor performance measure and one or more instance parameters that are available as inputs to a second, stress-insensitive, transistor model. The second transistor model may for example be the same as the first model, with its stress sensitivity disabled. Thereafter, a substitute stress analyzer can be used to determine a stress-adjusted value for the first performance measure, and the mathematical relationship can be used to convert that value into specific values for the one or more instance parameters. These values are then provided to the second transistor model for use in simulating the characteristics of the particular transistor during circuit simulation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.