Apparatus and method for extending a microprocessor instruction set
US7543134B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2004 |
| Grant date | Jun 2, 2009 |
| Priority date | — |
| Expiry date | Aug 21, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30185
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for extending a microprocessor instruction set is provided. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended instruction has an extended prefix and an extended instruction tag. The extended prefix directs that an architectural extension be employed in the execution of an operation prescribed by the extended instruction. The extended instruction tag indicates the extended instruction prefix, where the extended instruction tag is an otherwise architecturally specified opcode within the microprocessor instruction set. The extended execution logic is coupled to the translation logic, and receives the corresponding micro instructions, and employs the architectural extension in the execution of the operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.