Dual metal silicide scheme using a dual spacer process

US7544575B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Olubunmi O. Adetutu · Austin, US
• Dharmesh Jawarani · Round Rock, US
• Randy W. Cotton · Pflugerville, US

Key dates

• Filing date: Jan 19, 2006
• Grant date: Jun 9, 2009
• Expiry date: Mar 2, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/662

Abstract

A semiconductor process and apparatus provide a polysilicon structure (10) and source/drain regions (12, 14) formed adjacent thereto in which a dual silicide scheme is used to form first silicide regions in the polysilicon, source and drain regions (30, 32, 34) using a first metal (e.g., cobalt). After forming sidewall spacers (40, 42), a second metal (e.g., nickel) is used to form second silicide regions in the polysilicon, source and drain regions (60, 62, 64) to reduce encroachment by the second silicide in the source/drain (62, 64) and to reduce resistance in the polysilicon structure caused by agglomeration and voiding from the first silicide (30).