MOS varactor with segmented gate doping
US7545007B2 · kind B2 · utility
12Cited by
17References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 8, 2005 |
| Grant date | Jun 9, 2009 |
| Priority date | — |
| Expiry date | Oct 27, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/217
Abstract
A MOS varactor is formed having a gate electrode comprising at least two abutting oppositely doped regions shorted together, in which the two regions are implanted simultaneously with source/drain implants for first and second types of transistor; at least one contact to a lower electrode is also formed simultaneously with the source/drain implants for the first type of transistor; the varactor insulator is formed simultaneously with the gate insulator for one type of transistor; and the lower electrode is formed simultaneously with a well for the first type of transistor, so that no additional mask is required.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.