Method and apparatus for leakage current reduction
US7545177B1 · kind B1 · utility
9Cited by
8References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2007 |
| Grant date | Jun 9, 2009 |
| Priority date | — |
| Expiry date | Mar 21, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0016
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Leakage current reduction from a logic block is implemented via power gating transistors that exhibit increased gate oxide thickness as compared to the thin-oxide devices of the power gated logic block. Increased gate oxide further allows increased gate to source voltage differences to exist on the power gating devices, which enhances performance and reduces gate leakage even further. Placement of the power gating transistors in proximity to other increased gate oxide devices minimizes area penalties caused by physical design constraints of the semiconductor die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.