Method of enhancing drive current in a transistor
US7547596B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 1, 2007 |
| Grant date | Jun 16, 2009 |
| Priority date | — |
| Expiry date | Aug 1, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0184
Abstract
A method of manufacturing a semiconductor device includes forming transistors including gate electrodes and source/drain regions over a substrate. A protective layer is placed over the source/drain regions and the gate electrodes. A portion of the protective layer is removed to expose a portion of the gate electrodes. The exposed portions of the gate electrodes are amorphized, and remaining portions of the protective layer located over the source/drain regions are removed. A stress memorization layer is formed over the gate electrodes, and the substrate is annealed in the presence of the stress memorization layer to at least reduce an amorphous content of the gate electrodes. The stress memorization layer is removed subsequent to the annealing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.