Soft errors handling in EEPROM devices
US7548461B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2004 |
| Grant date | Jun 16, 2009 |
| Priority date | — |
| Expiry date | May 4, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.