Latch placement for high performance and low power circuits
US7549137B2 · kind B2 · utility
37Cited by
4References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2006 |
| Grant date | Jun 16, 2009 |
| Priority date | — |
| Expiry date | Jul 26, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A novel iterative latch placement scheme wherein the latches are gradually pulled by increasing attraction force until they are eventually placed next to a clock distribution structure such as a local clock buffer (LCB). During the iterations, timing optimizations such as gate sizing and re-buffering are invoked in order to keep the timing estimation accurate. By applying the iterative clock net weighting adjustment, the present invention allows tighter interaction between logic placement and clock placement which leads to higher quality timing and significant power savings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.