Patterned plasma treatment to improve distribution of underfill material
US7550314B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2006 |
| Grant date | Jun 23, 2009 |
| Priority date | — |
| Expiry date | Sep 12, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A patterned plasma treatment may be provided on the chip and/or the substrate to enhance the distribution of underfill material between the chip and the substrate. The underfill material is typically dispensed after the chip is electrically connected to the substrate. The chip may be electrically connected to the substrate by an array of solder bumps, as one example. The underfill material is draw into a gap between the chip and the substrate by a capillary action. The patterned plasma-treated area formed on the chip and/or on the substrate may cause greater capillary force on the underfill material, as compared to non-plasma-treated areas. Such patterned plasma-treatment area may be designed and laid out to provide for more or better control of the underfill distribution between the chip and substrate while forming a chip package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.