Silicon rich barrier layers for integrated circuit devices
US7550340B2 · kind B2 · utility
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8References
13Claims
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Key dates
| Filing date | May 14, 2008 |
| Grant date | Jun 23, 2009 |
| Priority date | — |
| Expiry date | May 14, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices and memory cells are formed using silicon rich barrier layers to prevent diffusion of dopants from differently doped polysilicon films to overlying conductive layers or to substrates. A polycilicide gate electrode structure may be formed using the silicon rich barrier layers. Methods of forming the semiconductor devices and memory cells are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.