Electroless plating of metal caps for chalcogenide-based memory devices
US7550380B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2007 |
| Grant date | Jun 23, 2009 |
| Priority date | — |
| Expiry date | Jan 29, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8825
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a metal cap over a conductive interconnect in a chalcogenide-based memory device is provided and includes, forming a layer of a first conductive material over a substrate, depositing an insulating layer over the first conductive material and the substrate, forming an opening in the insulating layer to expose at least a portion of the first conductive material, depositing a second conductive material over the insulating layer and within the opening, removing portions of the second conductive material to form a conductive area within the opening, recessing the conductive area within the opening to a level below an upper surface of the insulating layer, forming a cap of a third conductive material over the recessed conductive area within the opening, depositing a stack of a chalcogenide based memory cell material over the cap, and depositing a conductive material over the chalcogenide stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.