Method for maintaining atomicity of instruction sequence to access a number of cache lines during proactive synchronization within a computer system
US7552290B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 23, 2006 |
| Grant date | Jun 23, 2009 |
| Priority date | — |
| Expiry date | Apr 24, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for maintaining atomicity of a sequence of instructions includes a processor requesting exclusive access to a given memory resource. The request may include executing a critical section of code having memory reference instructions each including a LOCK prefix, and the memory reference instructions may be followed by an ACQUIRE instruction. The method also includes comparing each memory address of the critical section of code to each address of sets of addresses in response to execution of the ACQUIRE instruction. Each address of the sets of addresses corresponds to a respective memory resource to which a requester has exclusive access. In response to any memory address of the critical section of code matching any address of the sets of addresses, the method includes causing the ACQUIRE instruction to fail, and inhibiting modifying data corresponding to any memory address in an atomic phase of the critical section of code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.