Memory mapped input/output virtualization
US7552436B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 2003 |
| Grant date | Jun 23, 2009 |
| Priority date | — |
| Expiry date | Jul 13, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/206
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of performing memory mapped input output operations to an alternate address space comprising: establishing a first instruction directed to a first memory mapped input output alternate address space associated with an adapter to store data in accordance with a definition of a z/Architecture; establishing a second instruction directed to the first memory mapped input output alternate address space associated with an adapter to load data in accordance with a definition of a z/Architecture; allocating at least one of a real resource and a virtual resource associated with the first alternate address space to a process; ensuring that the selected process corresponds with the process to which the resource is allocated. The process issues at least one of the first instruction and the second instruction and thereby causes execution of at least one of the store and load with the first alternate address space.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.