Using implanted poly-1 to improve charging protection in dual-poly process
US7553727B2 · kind B2 · utility
1Cited by
3References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2007 |
| Grant date | Jun 30, 2009 |
| Priority date | — |
| Expiry date | Apr 24, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows a first polysilicon layer to be selectively doped subsequent to deposition of the second polysilicon layer. The doping increases the conductivity of the first polysilicon layer which can achieve a more robust charging protection for multi-bit core array and a more uniform distribution of charge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.