Integration scheme for constrained SEG growth on poly during raised S/D processing
US7553732B1 · kind B1 · utility
8Cited by
99References
20Claims
0Family size
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Key dates
| Filing date | Jun 13, 2005 |
| Grant date | Jun 30, 2009 |
| Priority date | — |
| Expiry date | Jan 13, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for constraining lateral growth of gate caps formed during an epitaxial silicon growth process to achieve raised source/drain regions on poly silicon is presented. The method is appropriate for integration into a manufacturing process for integrated circuit semiconductor devices. The method utilizes selective etch processes, dependant upon the material comprising the protective layer (hard mask) over the gate and the material of the spacers, e.g., oxide mask/nitride spacers, or nitride mask/oxide spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.