Symmetric blocking transient voltage suppressor (TVS) using bipolar transistor base snatch
US7554839B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 30, 2006 |
| Grant date | Jun 30, 2009 |
| Priority date | — |
| Expiry date | Aug 9, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49002
Abstract
A symmetrical blocking transient voltage suppressing (TVS) circuit for suppressing a transient voltage includes an NPN transistor having a base electrically connected to a common source of two transistors whereby the base is tied to a terminal of a low potential in either a positive or a negative voltage transient. The two transistors are two substantially identical transistors for carrying out a substantially symmetrical bi-directional clamping a transient voltage. These two transistors further include a first and second MOSFET transistors having an electrically interconnected source. The first MOSFET transistor further includes a drain connected to a high potential terminal and a gate connected to the terminal of a low potential and the second MOSFET transistor further includes a drain connected to the terminal of a low potential terminal and a gate connected to the high potential terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.