Three-dimensional memory devices and methods of manufacturing and operating the same
US7554873B2 · kind B2 · utility
32Cited by
6References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2006 |
| Grant date | Jun 30, 2009 |
| Priority date | — |
| Expiry date | Jan 5, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/77
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a plurality of planes of memory arrays, each memory array including a plurality of memory cells. The memory device also includes a plurality of word lines and bit lines coupled to the memory cells in each plane, and at least one transistor to select at least one of the memory arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.