Method and apparatus for maintaining synchronization between layout clones
US7555739B1 · kind B1 · utility
35Cited by
3References
33Claims
0Family size
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Key dates
| Filing date | Aug 17, 2006 |
| Grant date | Jun 30, 2009 |
| Priority date | — |
| Expiry date | Apr 13, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for maintaining synchronization between a plurality of layout clones of an integrated circuit design, wherein each layout clone comprises at least one figure. The method comprises tracking relationships between equivalent figures of the plurality of layout clones, wherein the plurality of layout clones are associated with one another within an equivalence group and propagating an edit made in one of the layout clones within an equivalence group to the other layout clones within the equivalence group.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.