Recessed gate structure and method for preparing the same
US7557407B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 18, 2006 |
| Grant date | Jul 7, 2009 |
| Priority date | — |
| Expiry date | Jun 20, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/518
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A recessed gate structure comprises a semiconductor substrate, a recess positioned in the semiconductor substrate, a gate oxide layer positioned in the recess and a conductive layer positioned on the gate oxide layer, wherein the semiconductor substrate has a multi-step structure in the recess. The thickness of the gate oxide layer on one step surface can be different from that on another step surface of the multi-step structure. In addition, the recessed gate structure further comprises a plurality of doped regions positioned in the semiconductor substrate under the multi-step structure, and these doped regions may use different dosages and different types of dopants. There is a carrier channel in the semiconductor substrate under the recessed gate structure and the overall channel length of the carrier channel is substantially the summation of the lateral width and twice of the vertical depth of the recessed gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.