Memory cell for content-addressable memory
US7558095B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | May 2, 2007 |
| Grant date | Jul 7, 2009 |
| Priority date | — |
| Expiry date | Aug 14, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell for use in a content-addressable memory comprises a first latch and a second latch. The first latch is operative to store a first bit associated with a first stored word, while the second latch is operative to store a second bit associated with a second stored word. The first and second latches collectively comprise a plurality of latch transistors. Each of the latch transistors comprises a respective channel. The channels of the latch transistors are oriented in substantially the same direction, resulting in a very compact memory cell implementation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.