Memory controller with staggered request signal output
US7558150B2 · kind B2 · utility
13Cited by
9References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2007 |
| Grant date | Jul 7, 2009 |
| Priority date | — |
| Expiry date | Feb 15, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller having a time-staggered request signal output. A first timing signal is generated with a phase offset relative to a first clock signal in accordance with a first programmed value, and a second timing signal is generated with a phase offset relative to the first clock signal in accordance with a second programmed value. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.