Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor
US7558939B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2005 |
| Grant date | Jul 7, 2009 |
| Priority date | — |
| Expiry date | Dec 28, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/681
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A three-tiered TLB architecture in a multithreading processor that concurrently executes multiple instruction threads is provided. A macro-TLB caches address translation information for memory pages for all the threads. A micro-TLB caches the translation information for a subset of the memory pages cached in the macro-TLB. A respective nano-TLB for each of the threads caches translation information only for the respective thread. The nano-TLBs also include replacement information to indicate which entries in the nano-TLB/micro-TLB hold recently used translation information for the respective thread. Based on the replacement information, recently used information is copied to the nano-TLB if evicted from the micro-TLB.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.