Method of preparing active silicon regions for CMOS or other devices

US7560358B1 · kind B1 · utility

Assignee

• Intel Corporation · US

Inventors

• Seiyon Kim · Portland, US
• Peter L. D. Chang · Portland, US
• Ibrahim Ban · Beaverton, US
• Willy Rachmady · Beaverton, US

Key dates

• Filing date: Dec 31, 2007
• Grant date: Jul 14, 2009
• Expiry date: Jan 10, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201

Abstract

A method of preparing active silicon regions for CMOS or other devices includes providing a structure including a silicon substrate (210, 410) having formed thereon first and second silicon diffusion lines (110, 420), both of which include first and second silicon layers (211, 213, 421, 423), a silicon germanium layer (212, 422), and a mask layer (214, 424). The method further includes forming an oxide layer (430) in first and second regions of the structure, forming a polysilicon layer (510) over the oxide layer, removing the polysilicon layer from the first region and depositing oxide (610) therein in order to form an oxide anchor, removing the polysilicon layer from the second region, removing the silicon germanium layer, filling the first and second gaps with an electrically insulating material (910), and depositing oxide in the second region.