Method of forming gate stack for semiconductor electronic device
US7560361B2 · kind B2 · utility
14Cited by
12References
38Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2004 |
| Grant date | Jul 14, 2009 |
| Priority date | — |
| Expiry date | Apr 21, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a gate stack for semiconductor electronic devices utilizing wafer bonding of at least one structure containing a high-k dielectric material is provided. The method of the present invention includes a step of first selecting a first and second structure having a major surface respectively. In accordance with the present invention, at least one, or both, of the first and second structures includes at least a high-k dielectric material. Next, the major surfaces of the first and second structures are bonded together to provide a bonded structure containing at least the high-k dielectric material of a gate stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.