Self-aligned pitch reduction
US7560388B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2005 |
| Grant date | Jul 14, 2009 |
| Priority date | — |
| Expiry date | Sep 30, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0338
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method providing features in a dielectric layer is provided. A sacrificial layer is formed over the dielectric layer. A set of sacrificial layer features is etched into the sacrificial layer. A first set of dielectric layer features is etched into the dielectric layer through the sacrificial layer. The first set of dielectric layer features and the set of sacrificial layer features are filled with a filler material. The sacrificial layer is removed. The widths of the spaces between the parts of the filler material are shrunk with a shrink sidewall deposition. A second set of dielectric layer features is etched into the dielectric layer through the shrink sidewall deposition. The filler material and shrink sidewall deposition are removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.