Method for fabricating group III nitride compound semiconductors and group III nitride compound semiconductor devices
US7560725B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2005 |
| Grant date | Jul 14, 2009 |
| Priority date | — |
| Expiry date | Sep 17, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/8215
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A first Group III nitride compound semiconductor layer 31 is etched, to thereby form an island-like structure such as a dot-like, stripe-shaped, or grid-like structure, so as to provide a trench/post. Thus, a second Group III nitride compound layer 32 can be epitaxially grown, vertically and laterally, from a top surface of the post and a sidewall/sidewalls of the trench serving as a nucleus for epitaxial growth, to thereby bury the trench and also grow the layer in the vertical direction. In this case, propagation of threading dislocations contained in the first Group III nitride compound semiconductor layer 31 can be prevented in the upper portion of the second Group III nitride compound semiconductor 32 that is formed through lateral epitaxial growth. As a result, a region having less threading dislocations is formed at the buried trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.