Cycling improvement using higher erase bias
US7561471B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2007 |
| Grant date | Jul 14, 2009 |
| Priority date | — |
| Expiry date | Aug 20, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods of erasing flash memory cells are provided that improve erase cycling speed and reliability. One embodiment comprises interactively applying a stepped or ramped drain voltage pattern to a drain of the memory cells and a pulsed gate voltage pattern to a gate of the memory cells for a predetermined number of gate pulses or until all the memory cells are erased. In another embodiment, an erase bias circuit is provided for erasing a sector of flash memory cells, the circuit comprising row and column decoders that selects wordline rows and columns of cells, respectively, a supply bias arrangement that provides source and drain supply voltages for the sector, and a patterned pulse bias arrangement configured to provide a pulsed gate voltage pattern to gates of the cells selected by the row decoder and a drain voltage pattern to the drains of the cells selected by the column decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.