Program verifying method and programming method of flash memory device
US7561474B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2007 |
| Grant date | Jul 14, 2009 |
| Priority date | — |
| Expiry date | Dec 27, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3436
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A duel program verify operation is performed using first and second verify voltages. In order to reduce the width of a threshold voltage distribution during an incremental step pulse program implementation, data of a corresponding memory cell are verified twice using the first verify voltage and the second verify voltage. During a second verify operation using the second verify voltage, a sensing current is adjusted by controlling voltages applied as a bit line select signal and an evaluation time period. Therefore, the threshold voltage of the memory cell can be measured higher or lower than its actual value and the width of a threshold voltage distribution is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.