Defective block isolation in a non-volatile memory system
US7561482B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2006 |
| Grant date | Jul 14, 2009 |
| Priority date | — |
| Expiry date | Mar 27, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus provide an improved identification and isolation of defective blocks in non-volatile memory devices having a plurality of user accessible blocks of non-volatile storage elements where each block also has an associated defective block latch. The method provides for sensing each defective block latch to determine whether the defective block latch was set due to a defect, and storing, in temporary on chip memory, address data corresponding to each set latch. The method further involves retrieving the address data and disabling defective blocks based upon the address data. A non-volatile memory device is also described having a controller which senses the defective block latches, stores address data for each block having a set latch, and subsequently retrieves the stored address data to set the defective block latches based upon the address data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.