Edge recognition based high voltage pseudo layer verification methodology for mix signal design layout
US7562315B2 · kind B2 · utility
1Cited by
4References
17Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 8, 2005 |
| Grant date | Jul 14, 2009 |
| Priority date | — |
| Expiry date | Dec 12, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Validation of at least some of a proposed semiconductor design layout is disclosed. According to one or more aspects of the present invention, a first voltage dependent design rule is applied to an edge of an area of the layout if the edge is not covered by a pseudo layer. A second voltage dependent design rule is, on the other hand, applied to the edge of the area if the edge is covered by the pseudo layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.