Method for etching single-crystal semiconductor selective to amorphous/polycrystalline semiconductor and structure formed by same
US7563670B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2006 |
| Grant date | Jul 21, 2009 |
| Priority date | — |
| Expiry date | Dec 2, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/395
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a vertical DRAM device. A lower trench is filled with polycrystalline or amorphous semiconductor for a capacitor. An upper trench portion has exposed sidewalls of single-crystal semiconductor. The method then includes etching the single-crystal semiconductor sidewalls to widen the upper trench portion beyond the exposed upper surface of the semiconductor fill of the capacitor to form exposed regions of single-crystal semiconductor on a bottom portion of the upper trench adjacent to the exposed upper surface of the semiconductor fill. A trench top insulating layer is deposited on the bottom portion of the upper trench, over the upper surface of the semiconductor fill and over the adjacent regions of single-crystal semiconductor. The method then includes forming a vertical gate dielectric layer, wherein the trench top insulating layer extends below the vertical gate insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.