Memory device and methods for its fabrication
US7564091B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2008 |
| Grant date | Jul 21, 2009 |
| Priority date | — |
| Expiry date | Aug 27, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
A semiconductor memory device and a method for its fabrication are provided. In accordance with one embodiment of the invention the method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is etched to form an undercut opening beneath an edge of the gate electrode and the undercut opening is filled with a layered structure comprising a charge trapping layer sandwiched between layers of oxide and nitride. A region of the semiconductor substrate is impurity doped to form a bit line aligned with the gate electrode, and a conductive layer is deposited and patterned to form a word line coupled to the gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.