Memory device with retained indicator of read reference level
US7564716B2 · kind B2 · utility
6Cited by
5References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2006 |
| Grant date | Jul 21, 2009 |
| Priority date | — |
| Expiry date | Dec 30, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A read reference level of a plurality of read reference is determined for a set of bit cells of a non-volatile memory array. An indicator of the read reference level is stored in a non-volatile storage location associated with the set of bit cells. The indicator of the read reference level is accessed in response to a read access operation to the set of bit cells and a value stored at a memory location of the set of bit cells is sensed based on the indicator of the read reference level, whereby the memory location of the set of bit cells is associated with the read access operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.