Manufacturing method for an integrated semiconductor structure

US7566611B2 · kind B2 · utility

Assignee

• Qimonda AG · DE

Inventors

• Peter Baars · Dresden, DE
• Klaus Muemmler · Dresden, DE
• Stefan Tegen · Dresden, DE
• Daniel Koehler · Althengstett, DE
• Joern Regul · Dresden, DE

Key dates

• Filing date: May 31, 2006
• Grant date: Jul 28, 2009
• Expiry date: Dec 20, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/053

Abstract

The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of providing a semiconductor substrate having a plurality of gate stacks in a memory cell region and at least one gate stack in a peripheral device region; forming caps made of one or more layers of a cap material over said plurality of gate stacks in said memory cell region and over said at least one gate stack in said peripheral device region; depositing a first protective layer made of carbon or made of a carbon containing material over said memory cell region and peripheral device region; forming a mask layer on said first protective layer in said memory cell region; exposing said cap of said at least one gate stack in said peripheral device region by removing said first protective layer in said peripheral device region in an etch step wherein said mask layer acts as a mask in said memory cell region; removing said mask layer and said first protective layer from said memory cell region; forming a first contact hole between two neighboring gate stacks in said memory cell region, said first contact hole exposing a contact area; forming at least one other contact ho…