DRAM including a vertical surround gate transistor

US7566620B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventor

• Todd R. Abbott · Boise, US

Key dates

• Filing date: Jul 31, 2006
• Grant date: Jul 28, 2009
• Expiry date: Jul 31, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/488

Abstract

DRAM memory cells having a feature size of less than about 4F2 include vertical surround gate transistors that are configured to reduce any short channel effect on the reduced size memory cells. In addition, the memory cells may advantageously include reduced resistance word line contacts and reduced resistance bit line contacts, which may increase a speed of the memory device due to the reduced resistance of the word line and bit line contacts.