Lock and key structure for three-dimensional chip connection and process thereof
US7566632B1 · kind B1 · utility
13Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2008 |
| Grant date | Jul 28, 2009 |
| Priority date | — |
| Expiry date | Feb 6, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method positions a first wafer with respect to a second wafer such that key studs on the first wafer are fit (positioned) within lock openings in the second wafer. The key studs contact conductors within the second wafer. The edges of the first wafer are tacked to the edges of the second wafer. Then the wafers are pressed together and heat is applied to bond the wafers together. One feature of embodiments herein is that because the lock openings extend through an outer oxide (instead of a polyimide) the first wafer can be attached to the second wafer by using processing that occurs in the middle-of-the-line (MOL).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.