Method for chip singulation
US7566634B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2005 |
| Grant date | Jul 28, 2009 |
| Priority date | — |
| Expiry date | Aug 10, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3043
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention is related to a method for singulating chips from a stack of layers, such as the layers on a wafer or substrate. The stack of layers includes a front end of line (FEOL) layer upon the substrate layer, with the substrate layer having a first surface and a second surface. The FEOL is positioned on top of the first surface, and a back end of line (BEOL) layer is positioned on top of the FEOL. The method includes etching singulating trenches through the BEOL, through the FEOL and at least partially through the substrate layer, depositing a passivation layer on the stack provided with singulating trenches, whereby the sidewalls of the etched singulating trenches are at least partially passivated. Dicing, such as blade dicing, laser dicing or trench etch dicing is performed, releasing the chip from the stack of layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.