Integration process for fabricating stressed transistor structure
US7566655B2 · kind B2 · utility
15Cited by
16References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2006 |
| Grant date | Jul 28, 2009 |
| Priority date | — |
| Expiry date | Jan 30, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
A process flow integration scheme employs one or more techniques to control stress in a semiconductor device formed thereby. In accordance with one embodiment, cumulative stress contributed by RTP of a nitride spacer and polysilicon gate, and subsequent deposition of a high stress etch stop layer, enhance strain and improve device performance. Germanium may be deposited or implanted into the gate structure in order to facilitate stress control.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.