Flash memory array having control/decode circuitry for disabling top gates of defective memory cells
US7567458B2 · kind B2 · utility
5Cited by
6References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2005 |
| Grant date | Jul 28, 2009 |
| Priority date | — |
| Expiry date | May 17, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/832
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.