Method and apparatus for testing embedded cores

US7568141B2 · kind B2 · utility

Assignees

• Intel Corporation · US
• Analog Devices, Inc. · US

Inventors

• Sankaran M. Menon · Austin, US
• Luis A. Basto · Austin, US
• Tien Dinh · Cedar Park, US
• Thomas Tomazin · Austin, US
• Juan Guillermo Revilla · Cary, US

Key dates

• Filing date: Dec 21, 2007
• Grant date: Jul 28, 2009
• Expiry date: Dec 21, 2027

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2029/0401
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

The inputs to an embedded core, e.g., the core terminals, may not be directly connected to pins on the SoC. The lack of direct access to an embedded core's terminals may complicate testing of the embedded core. A test wrapper including boundary scan test (BST) cells may be used to test an embedded core. Dual function BST/ATPG (Automatic Test Pattern Generation) cells may be used to perform both BST and ATPG tests on embedded cores.