Ramptime propagation on designs with cycles
US7568175B2 · kind B2 · utility
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32References
5Claims
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Key dates
| Filing date | Jun 1, 2007 |
| Grant date | Jul 28, 2009 |
| Priority date | — |
| Expiry date | Aug 22, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for calculating ramptime propagation for integrated circuit layout patterns having pins interconnected in an oriented graph in one or more closed loops is described. Ramptime values are calculated for a first set of the pins, which are not connected to a closed loop while leaving a second set of the pins with unknown ramptime values. One or more closed loops are identified by backtracking from the pins in the second set with unknown ramptime values. A ramptime value for each pin in the one or more closed loops is calculated iteratively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.