Fabricating a memory cell array
US7569878B2 · kind B2 · utility
12Cited by
4References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2005 |
| Grant date | Aug 4, 2009 |
| Priority date | — |
| Expiry date | Feb 24, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
Abstract
A DRAM memory cell array is fabricated such that, for each memory cell of the array, the gate electrode is initially produced such that it is insulated from all the other gate electrodes assigned to a certain word line, and is only connected to the other gate electrodes assigned to the corresponding word line via the word line in a subsequent step.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.