Semiconductor integrated circuit device with reduced leakage current
US7569881B2 · kind B2 · utility
7Cited by
4References
18Claims
0Family size
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Key dates
| Filing date | Apr 9, 2008 |
| Grant date | Aug 4, 2009 |
| Priority date | — |
| Expiry date | Apr 9, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.