Semiconductor device and manufacturing method thereof
US7569921B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2006 |
| Grant date | Aug 4, 2009 |
| Priority date | — |
| Expiry date | Jul 2, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device has a plurality of bare chips stacked on at least one of first and second main surfaces oppositely arranged on a support substrate, spacers arranged between two bare chips arranged adjacently in up and down direction among the plurality of bare chips, and inner leads which are arranged at both sides in a horizontal direction of the support substrate and are connected to pads of the bare chips via bonding wires, wherein the bonding wires which connect the pads of the bare chips at one end side of the spacers to the corresponding inner leads, are arranged not to contact the bare chip at the other end side of the same spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.