Device and method to reduce wordline RC time constant in semiconductor memory devices
US7570504B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 15, 2001 |
| Grant date | Aug 4, 2009 |
| Priority date | — |
| Expiry date | Jan 11, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device and a method of making and using a semiconductor memory device containing a word line design, which is used in ultra-large scale integrated (ULSI) circuits, that produces a device with a lower RC time constant than devices formed using prior art techniques. In one embodiment of the invention low resistivity metal strapping layers are attached to alternating halves of wordlines in a single memory array. The alternating pattern allows the low resistivity of the strapping layers to be utilized without introducing significant negative capacitive resistance effects due to strapping layers being too close to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.