Quasi-differential read operation
US7570507B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 29, 2007 |
| Grant date | Aug 4, 2009 |
| Priority date | — |
| Expiry date | Jun 29, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes an array portion of resistive memory cells comprising a plurality of bit line pairs. The device further includes a read circuit operably associated with a first charged line, wherein the read circuit comprises a precharge circuit configured to charge a first line at a first rate, and to charge a second line at a second rate, the first and second charge rates based on a state of a memory cell coupled between the respective lines. The read circuit may further include a ground circuit configured to pull the respective lines to a ground potential, and a sense circuit coupled to the line pair configured to sense a differential voltage between the line pair in response to the state of the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.