Generation of multiple checkpoints in a processor that supports speculative execution
US7571304B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2005 |
| Grant date | Aug 4, 2009 |
| Priority date | — |
| Expiry date | Dec 2, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention provides a system which creates multiple checkpoints in a processor that supports speculative-execution. The system starts by issuing instructions for execution in program order during execution of a program in a normal-execution mode. Upon encountering a launch condition during an instruction which causes a processor to enter execute-ahead mode, the system performs an initial checkpoint and commences execution of instructions in execute-ahead mode. Upon encountering a predefined condition during execute-ahead mode, the system generates an additional checkpoint and continues to execute instructions in execute-ahead mode. Generating the additional checkpoint allows the processor to return to the additional checkpoint, instead of the previous checkpoint, if the processor subsequently encounters a condition that requires the processor to return to a checkpoint.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.