Method for generating a design rule map having spatially varying overlay budget
US7571422B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2007 |
| Grant date | Aug 4, 2009 |
| Priority date | — |
| Expiry date | Sep 18, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/70533
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The invention is a method for generating a design rule map having a spatially varying overlay error budget. Additionally, the spatially varying overlay error budget can be employed to determine if wafers are fabricated in compliance with specifications. In one approach a design data file that contains fabrication process information and reticle information is processed using design rules to obtain a design map with a spatially varying overlay error budget that defines a localized tolerance to overlay errors for different spatial locations on the design map. This spatially varying overlay error budget can be used to disposition wafers. For example, overlay information obtained from measured metrology targets on a fabricated wafer are compared with the spatially varying overlay error budget to determine if the wafer overlay satisfies the required specification.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.