Methods for transistor formation using selective gate implantation
US7572693B2 · kind B2 · utility
0Cited by
11References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2006 |
| Grant date | Aug 11, 2009 |
| Priority date | — |
| Expiry date | Jan 5, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods are disclosed for semiconductor device fabrication in which dopants are selectively implanted into transistor gate structures to counteract or compensate for dopant depletion during subsequent fabrication processing. A patterned implant mask is formed over a semiconductor device, which exposes at least a portion of the gate structure and covers the remaining upper surfaces of the device. Thereafter, dopants are selectively implanted in to the exposed gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.