Interconnect line selectively isolated from an underlying contact plug
US7573087B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 15, 2006 |
| Grant date | Aug 11, 2009 |
| Priority date | — |
| Expiry date | Sep 13, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A means for selectively electrically connecting an electrical interconnect line, such as a bit line of a memory cell, with an associated contact stud and electrically isolating the interconnect line from other partially underlying contact studs for other electrical features, such as capacitor bottom electrodes. The interconnect line can be formed partially-connected to all contact studs, thereby allowing the electrical features to be formed in closer proximity to one another for higher levels of integration, and in subsequent steps of fabrication, the contact studs associated with memory cell features other than the interconnect line can be isolated from the interconnect line by the removal of a silicide cap, or the selective etching of a portion of these contact studs, and the formation of an insulating sidewall between the non-selected contact stud and the interconnect line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.